/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 *
 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __CSIC__TOP__REG__I__H__
#define __CSIC__TOP__REG__I__H__

/*
 * Detail information of registers
 */
 /*
 *CSIC TOP registers
 */
#define CSIC_TOP_EN_REG_OFF			0X000
#define CSIC_TOP_EN				0
#define CSIC_TOP_EN_MASK			(0X1 << CSIC_TOP_EN)
#define CSIC_BIST_MODE_EN			2
#define CSIC_BIST_MODE_EN_MASK			(0X1 << CSIC_BIST_MODE_EN)
#define CSIC_ISP_BRIDGE_EN			3
#define CSIC_ISP_BRIDGE_EN_MASK			(0X1 << CSIC_ISP_BRIDGE_EN)
#define CSIC_SRAM_PWDN				8
#define CSIC_SRAM_PWDN_MASK			(0X1 << CSIC_SRAM_PWDN)
#define CSIC_ISP_F2S0_BRIDGE_CH_EN		12
#define CSIC_ISP_F2S0_BRIDGE_CH_EN_MASK		(0X1 << CSIC_ISP_F2S0_BRIDGE_CH_EN)
#define CSIC_ISP_S0F2_BRIDGE_CH_EN		16
#define CSIC_ISP_S0F2_BRIDGE_CH_EN_MASK		(0X1 << CSIC_ISP_S0F2_BRIDGE_CH_EN)
#define CSIC_ISP_BRIDGE_CH_EN_DISABLE		20
#define CSIC_ISP_BRIDGE_CH_EN_DISABLE_MASK	(0X1 << CSIC_ISP_BRIDGE_CH_EN_DISABLE)
#define CSIC_VER_EN				31
#define CSIC_VER_EN_MASK			(0X1 << CSIC_VER_EN)

#define CSIC_PTN_GEN_EN_REG_OFF			0X004
#define CSIC_PTN_GEN_EN				0
#define CSIC_PTN_GEN_EN_MASK			(0X1 << CSIC_PTN_GEN_EN)
#define CSIC_PTN_GEN_START			4
#define CSIC_PTN_GEN_START_MASK			(0X1 << CSIC_PTN_GEN_START)
#define CSIC_PTN_GEN_CYCLE			16
#define CSIC_PTN_GEN_CYCLE_MASK			(0XFF << CSIC_PTN_GEN_CYCLE)

#define CSIC_PTN_CTRL_REG_OFF			0X008
#define CSIC_PTN_CLK_DIV			8
#define CSIC_PTN_CLK_DIV_MASK			(0X3 << CSIC_PTN_CLK_DIV)
#define CSIC_PTN_MODE				16
#define CSIC_PTN_MODE_MASK			(0XF << CSIC_PTN_MODE)
#define CSIC_PTN_DATA_WIDTH			20
#define CSIC_PTN_DATA_WIDTH_MASK		(0X3 << CSIC_PTN_DATA_WIDTH)
#define CSIC_PTN_PORT_SEL			24
#define CSIC_PTN_PORT_SEL_MASK			(0X7 << CSIC_PTN_PORT_SEL)

#define CSIC_PTN_VBLANK_CYCLE_REG       0X010
#define CSIC_PTN_VBANK_CYCLE            0
#define CSIC_PTN_VBANK_CYCLE_MASK       (0XFFFFF << CSIC_PTN_VBANK_CYCLE)

#define CSIC_PTN_LEN_REG_OFF			0X020
#define CSIC_PTN_ADDR_REG_OFF			0X024
#define CSIC_PTN_SIZE_REG_OFF			0X028
#define CSIC_PTN_WIDTH				0
#define CSIC_PTN_WIDTH_MASK			(0X1FFF << CSIC_PTN_WIDTH)
#define CSIC_PTN_HEIGHT				16
#define CSIC_PTN_HEIGHT_MASK			(0X1FFF << CSIC_PTN_HEIGHT)

#if IS_ENABLED(CONFIG_ARCH_SUN50IW3P1) || IS_ENABLED(CONFIG_ARCH_SUN50IW6P1)
#define CSIC_ISP0_IN0_REG_OFF			0X030
#define CSIC_ISP0_IN1_REG_OFF			0X034
#define CSIC_ISP0_IN2_REG_OFF			0X038
#define CSIC_ISP0_IN3_REG_OFF			0X03C

#define CSIC_ISP1_IN0_REG_OFF			0X040
#define CSIC_ISP1_IN1_REG_OFF			0X044
#define CSIC_ISP1_IN2_REG_OFF			0X048
#define CSIC_ISP1_IN3_REG_OFF			0X04C

#define CSIC_VIPP0_IN_REG_OFF			0X060
#define CSIC_VIPP1_IN_REG_OFF			0X064
#define CSIC_VIPP2_IN_REG_OFF			0X068
#define CSIC_VIPP3_IN_REG_OFF			0X06C

#define CSIC_FEATURE_REG_OFF			0X070
#define CSIC_VER_REG_OFF			0X074

#else

#define CSIC_ISP0_IN0_REG_OFF			0X030
#define CSIC_ISP0_IN1_REG_OFF			0X034
#define CSIC_ISP0_IN2_REG_OFF			0X038
#define CSIC_ISP0_IN3_REG_OFF			0X03C

#define CSIC_ISP1_IN0_REG_OFF			0X040
#define CSIC_ISP1_IN1_REG_OFF			0X044
#define CSIC_ISP1_IN2_REG_OFF			0X048
#define CSIC_ISP1_IN3_REG_OFF			0X04C

#define CSIC_ISP2_IN0_REG_OFF			0X050
#define CSIC_ISP2_IN1_REG_OFF			0X054
#define CSIC_ISP2_IN2_REG_OFF			0X058
#define CSIC_ISP2_IN3_REG_OFF			0X05C

#define CSIC_ISP3_IN0_REG_OFF			0X060
#define CSIC_ISP3_IN1_REG_OFF			0X064
#define CSIC_ISP3_IN2_REG_OFF			0X068
#define CSIC_ISP3_IN3_REG_OFF			0X06C

#define CSIC_VIPP0_IN_REG_OFF			0X0A0
#define CSIC_VIPP1_IN_REG_OFF			0X0A4
#define CSIC_VIPP2_IN_REG_OFF			0X0A8
#define CSIC_VIPP3_IN_REG_OFF			0X0AC
#define CSIC_VIPP4_IN_REG_OFF			0X0B0
#define CSIC_VIPP5_IN_REG_OFF			0X0B4
#define CSIC_VIPP6_IN_REG_OFF			0X0B8
#define CSIC_VIPP7_IN_REG_OFF			0X0BC
#define CSIC_VIPP8_IN_REG_OFF			0X0C0
#define CSIC_VIPP9_IN_REG_OFF			0X0C4
#define CSIC_VIPP10_IN_REG_OFF			0X0C8
#define CSIC_VIPP11_IN_REG_OFF			0X0CC

#if IS_ENABLED(CONFIG_ARCH_SUN8IW15P1) || IS_ENABLED(CONFIG_ARCH_SUN8IW16P1) || IS_ENABLED(CONFIG_ARCH_SUN8IW17P1) || IS_ENABLED(CONFIG_ARCH_SUN50IW9)
#define CSIC_FEATURE_REG_OFF			0X0F0
#define CSIC_VER_REG_OFF			0X0F4
#else
#define CSIC_MBUS_REQ_MAX			0x0F0
#define MCSI_MEM_REQ_MAX			0
#define MCSI_MEM_REQ_MAX_MASK			(0X1F << MCSI_MEM_REQ_MAX)
#define MCSI_MEM_1_REQ_MAX			8
#define MCSI_MEM_1_REQ_MAX_MASK			(0X1F << MCSI_MEM_1_REQ_MAX)
#define MISP_MEM_REQ_MAX			16
#define MISP_MEM_REQ_MAX_MASK			(0X1F << MISP_MEM_REQ_MAX)

#define CSIC_FEATURE_REG_OFF			0X1F0
#define CSIC_VER_REG_OFF			0X1F4
#endif
#endif

#define CSIC_FEATURE_RES0			0
#define CSIC_FEATURE_RES0_MASK			(0XFF << CSIC_FEATURE_RES0)
#define CSIC_DMA_NUM				8
#define CSIC_DMA_NUM_MASK			(0XF << CSIC_DMA_NUM)
#define CSIC_VIPP_NUM				12
#define CSIC_VIPP_NUM_MASK			(0XF << CSIC_VIPP_NUM)
#define CSIC_ISP_NUM				16
#define CSIC_ISP_NUM_MASK			(0XF << CSIC_ISP_NUM)
#define CSIC_NCSI_NUM				20
#define CSIC_NCSI_NUM_MASK			(0XF << CSIC_NCSI_NUM)
#define CSIC_MCSI_NUM				24
#define CSIC_MCSI_NUM_MASK			(0XF << CSIC_MCSI_NUM)
#define CSIC_PARSER_NUM				28
#define CSIC_PARSER_NUM_MASK			(0XF << CSIC_PARSER_NUM)

#define CSIC_VER_SMALL				0
#define CSIC_VER_SMALL_MASK			(0XFFF << CSIC_VER_SMALL)
#define CSIC_VER_BIG				12
#define CSIC_VER_BIG_MASK			(0XFFF << CSIC_VER_BIG)

#define CSIC_MULP_MODE_REG_OFF  		0X100
#define CSIC_MULP_EN				0
#define CSIC_MULP_EN_MASK			(0X1 << CSIC_MULP_EN)
#define CSIC_MULP_CS				8
#define CSIC_MULP_CS_MASK			(0XFF << CSIC_MULP_CS)
#define CSIC_MULP_STATUS			24
#define CSIC_MULP_STATUS_MASK			(0XFF << CSIC_MULP_STATUS)
#define CSIC_MULP_INT_REG_OFF   		0X104
#define CSIC_MULP_INT_EN			0
#define CSIC_MULP_INT_EN_MASK			(0X3 << CSIC_MULP_INT_EN)
#define CSIC_MULP_DONE_PD			16
#define CSIC_MULP_DONE_PD_MASK  		(0X1 << CSIC_MULP_DONE_PD)
#define CSIC_MULP_ERR_PD			17
#define CSIC_MULP_ERR_PD_MASK			(0X1 << CSIC_MULP_ERR_PD)
#define CSIC_MULP_INT_PD_MASK			(0X3 << CSIC_MULP_DONE_PD)

#define CSIC_CHANGE_FREQUENCY_CONFIGURATION_REG_OFF  	0X108
#define CSIC_CHFREQ_RST_EN				0
#define CSIC_CHFREQ_RST_EN_MASK				(0X1 << CSIC_CHFREQ_RST_EN)
#define CSIC_CHFREQ_ALLOW				1
#define CSIC_CHFREQ_ALLOW_MASK				(0X1 << CSIC_CHFREQ_ALLOW)
#define CSIC_CHFREQ_RDY_EN				3
#define CSIC_CHFREQ_RDY_EN_MASK				(0X1 << CSIC_CHFREQ_RDY_EN)
#define CSIC_CHFREQ_PAR2ISP_SEL_EN			16
#define CSIC_CHFREQ_PAR2ISP_SEL_EN_MASK			(0XFFFF << CSIC_CHFREQ_PAR2ISP_SEL_EN)

#define CSIC_CHANGE_FREQUENCY_CONFIGURATION1_REG_OFF  	0X10C
#define CSIC_CHFREQ_DDR_TIME				0
#define CSIC_CHFREQ_DDR_TIME_MASK			(0XFFFF << CSIC_CHFREQ_DDR_TIME)
#define CSIC_CHFREQ_WAIT_DONE_TIME			16
#define CSIC_CHFREQ_WAIT_DONE_TIME_MASK			(0XFFFF << CSIC_CHFREQ_WAIT_DONE_TIME)


#define CSIC_CHANGE_FREQUENCY_OBSERVATION_REG_OFF  	0X110
#define CSIC_CHFREQ_VBLANK_LENGTH			0
#define CSIC_CHFREQ_VBLANK_LENGTH_MASK			(0XFFFF << CSIC_CHFREQ_VBLANK_LENGTH)
#define CSIC_CHFREQ_FRM_DOBE_TIME			16
#define CSIC_CHFREQ_FRM_DOBE_TIME_MASK			(0XFFFF << CSIC_CHFREQ_FRM_DOBE_TIME)

#define CSIC_CHANGE_FREQUENCY_INT_REG_OFF  	0X114
#define CSIC_CHFREQ_FRM_STR_NUM_ERR_EN			0
#define CSIC_CHFREQ_FRM_STR_NUM_ERR_EN_MASK		(0X1 << CSIC_CHFREQ_FRM_STR_NUM_ERR_EN)
#define CSIC_CHFREQ_FRM_END_NUM_ERR_EN			1
#define CSIC_CHFREQ_FRM_END_NUM_ERR_EN_MASK		(0X1 << CSIC_CHFREQ_FRM_END_NUM_ERR_EN)
#define CSIC_CHFREQ_FRM_DONE_NUM_ERR_EN			2
#define CSIC_CHFREQ_FRM_DONE_NUM_ERR_EN_MASK		(0X1 << CSIC_CHFREQ_FRM_DONE_NUM_ERR_EN)

#define CSIC_BK_INTPOOL0_CFG0_REG_OFF	0X130
#define CSIC_BK_INT_POOL_EN				0
#define CSIC_BK_INT_POOL_EN_MASK		(0X1 << CSIC_BK_INT_POOL_EN)
#define CSIC_INT_SRC_SEL				1
#define CSIC_INT_SRC_SEL_MASK			(0X1 << CSIC_INT_SRC_SEL)
#define CSIC_TRIG_MOD					2
#define CSIC_TRIG_MOD_MASK				(0X1 << CSIC_TRIG_MOD)
#define CSIC_TRIG_LEVEL					4
#define CSIC_TRIG_LEVEL_MASK			(0X3F << CSIC_TRIG_LEVEL)
#define CSIC_TRIG_ID					10
#define CSIC_TRIG_ID_MASK				(0XF << CSIC_TRIG_ID)
#define CSIC_TRIG_CH					14
#define CSIC_TRIG_CH_MASK				(0X3 << CSIC_TRIG_CH)
/* write once to cfg all src mask */
#define CSIC_SRC_MSK_CFG_GROUP0			16
#define CSIC_SRC_MSK_CFG_GROUP0_MASK	(0XFFFF << CSIC_SRC_MSK_CFG_GROUP0)
#define CSIC_SRC_MSK_BK0_CH0			16
#define CSIC_SRC_MSK_BK0_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK0_CH0)
#define CSIC_SRC_MSK_BK0_CH1			17
#define CSIC_SRC_MSK_BK0_CH1_MASK		(0X1 << CSIC_SRC_MSK_BK0_CH1)
#define CSIC_SRC_MSK_BK0_CH2			18
#define CSIC_SRC_MSK_BK0_CH2_MASK		(0X1 << CSIC_SRC_MSK_BK0_CH2)
#define CSIC_SRC_MSK_BK0_CH3			19
#define CSIC_SRC_MSK_BK0_CH3_MASK		(0X1 << CSIC_SRC_MSK_BK0_CH3)
#define CSIC_SRC_MSK_BK1_CH0			20
#define CSIC_SRC_MSK_BK1_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK1_CH0)
#define CSIC_SRC_MSK_BK1_CH1			21
#define CSIC_SRC_MSK_BK1_CH1_MASK		(0X1 << CSIC_SRC_MSK_BK1_CH1)
#define CSIC_SRC_MSK_BK1_CH2			22
#define CSIC_SRC_MSK_BK1_CH2_MASK		(0X1 << CSIC_SRC_MSK_BK1_CH2)
#define CSIC_SRC_MSK_BK1_CH3			23
#define CSIC_SRC_MSK_BK1_CH3_MASK		(0X1 << CSIC_SRC_MSK_BK1_CH3)
#define CSIC_SRC_MSK_BK2_CH0			24
#define CSIC_SRC_MSK_BK2_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK2_CH0)
#define CSIC_SRC_MSK_BK3_CH0			28
#define CSIC_SRC_MSK_BK3_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK3_CH0)

#define CSIC_BK_INTPOOL0_CFG1_REG_OFF	0X134
/* write once to cfg all src mask */
#define CSIC_SRC_MSK_CFG_GROUP1			0
#define CSIC_SRC_MSK_CFG_GROUP1_MASK	(0XFFFFFFFF << CSIC_SRC_MSK_CFG_GROUP1)
#define CSIC_SRC_MSK_BK4_CH0			0
#define CSIC_SRC_MSK_BK4_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK4_CH0)
#define CSIC_SRC_MSK_BK5_CH0			4
#define CSIC_SRC_MSK_BK5_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK5_CH0)
#define CSIC_SRC_MSK_BK6_CH0			8
#define CSIC_SRC_MSK_BK6_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK6_CH0)
#define CSIC_SRC_MSK_BK6_CH1			9
#define CSIC_SRC_MSK_BK6_CH1_MASK		(0X1 << CSIC_SRC_MSK_BK6_CH1)
#define CSIC_SRC_MSK_BK6_CH2			10
#define CSIC_SRC_MSK_BK6_CH2_MASK		(0X1 << CSIC_SRC_MSK_BK6_CH2)
#define CSIC_SRC_MSK_BK6_CH3			11
#define CSIC_SRC_MSK_BK6_CH3_MASK		(0X1 << CSIC_SRC_MSK_BK6_CH3)
#define CSIC_SRC_MSK_BK7_CH0			12
#define CSIC_SRC_MSK_BK7_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK7_CH0)
#define CSIC_SRC_MSK_BK7_CH1			13
#define CSIC_SRC_MSK_BK7_CH1_MASK		(0X1 << CSIC_SRC_MSK_BK7_CH1)
#define CSIC_SRC_MSK_BK7_CH2			14
#define CSIC_SRC_MSK_BK7_CH2_MASK		(0X1 << CSIC_SRC_MSK_BK7_CH2)
#define CSIC_SRC_MSK_BK7_CH3			15
#define CSIC_SRC_MSK_BK7_CH3_MASK		(0X1 << CSIC_SRC_MSK_BK7_CH3)
#define CSIC_SRC_MSK_BK8_CH0			16
#define CSIC_SRC_MSK_BK8_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK8_CH0)
#define CSIC_SRC_MSK_BK9_CH0			20
#define CSIC_SRC_MSK_BK9_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK9_CH0)
#define CSIC_SRC_MSK_BK10_CH0			24
#define CSIC_SRC_MSK_BK10_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK10_CH0)
#define CSIC_SRC_MSK_BK11_CH0			28
#define CSIC_SRC_MSK_BK11_CH0_MASK		(0X1 << CSIC_SRC_MSK_BK11_CH0)

#define CSIC_BK_INT_FIFO0_REG_OFF		0X138
#define CSIC_INT_FIFO0_DATA				0
#define CSIC_INT_FIFO0_DATA_MASK		(0XFFFFFFFF << CSIC_INT_FIFO0_DATA)

#define CSIC_BK_INTPOOL0_OBS0_REG_OFF	0X13C
#define CSIC_FIFO_LEVEL					0
#define CSIC_FIFO_LEVEL_MASK			(0X7F << CSIC_FIFO_LEVEL)
#define CSIC_TRIG_TGT_LEVEL				16
#define CSIC_TRIG_TGT_LEVEL_MASK		(0X7F << CSIC_TRIG_TGT_LEVEL)

#define CSIC_BK_INTPOOL0_OBS1_REG_OFF	0X140
#define CSIC_ACCESS_DELAY				0
#define CSIC_ACCESS_DELAY_MASK			(0XFFFF << CSIC_ACCESS_DELAY)
#define CSIC_FULL_ACCESS_DELAY			16
#define CSIC_FULL_ACCESS_DELAY_MASK		(0XFFFF << CSIC_FULL_ACCESS_DELAY)

#define CSIC_BK_INTPOOL0_INT_EN0_REG_OFF	0X144
#define CSIC_FIFO_AVL_INT_EN				0
#define CSIC_FIFO_AVL_INT_EN_MASK			(0X1 << CSIC_FIFO_AVL_INT_EN)
#define CSIC_FIFO_FULL_INT_EN				1
#define CSIC_FIFO_FULL_INT_EN_MASK			(0X1 << CSIC_FIFO_FULL_INT_EN)
#define CSIC_BK0_CH0_INT_LOST_INT_EN		16
#define CSIC_BK0_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK0_CH0_INT_LOST_INT_EN)
#define CSIC_BK0_CH1_INT_LOST_INT_EN		17
#define CSIC_BK0_CH1_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK0_CH1_INT_LOST_INT_EN)
#define CSIC_BK0_CH2_INT_LOST_INT_EN		18
#define CSIC_BK0_CH2_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK0_CH2_INT_LOST_INT_EN)
#define CSIC_BK0_CH3_INT_LOST_INT_EN		19
#define CSIC_BK0_CH3_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK0_CH3_INT_LOST_INT_EN)
#define CSIC_BK1_CH0_INT_LOST_INT_EN		20
#define CSIC_BK1_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK1_CH0_INT_LOST_INT_EN)
#define CSIC_BK1_CH1_INT_LOST_INT_EN		21
#define CSIC_BK1_CH1_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK1_CH1_INT_LOST_INT_EN)
#define CSIC_BK1_CH2_INT_LOST_INT_EN		22
#define CSIC_BK1_CH2_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK1_CH2_INT_LOST_INT_EN)
#define CSIC_BK1_CH3_INT_LOST_INT_EN		23
#define CSIC_BK1_CH3_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK1_CH3_INT_LOST_INT_EN)
#define CSIC_BK2_CH0_INT_LOST_INT_EN		24
#define CSIC_BK2_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK2_CH0_INT_LOST_INT_EN)
#define CSIC_BK3_CH0_INT_LOST_INT_EN		28
#define CSIC_BK3_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK3_CH0_INT_LOST_INT_EN)

#define CSIC_BK_INTPOOL0_INT_EN1_REG_OFF	0X148
#define CSIC_BK4_CH0_INT_LOST_INT_EN		0
#define CSIC_BK4_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK4_CH0_INT_LOST_INT_EN)
#define CSIC_BK5_CH0_INT_LOST_INT_EN		4
#define CSIC_BK5_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK5_CH0_INT_LOST_INT_EN)
#define CSIC_BK6_CH0_INT_LOST_INT_EN		8
#define CSIC_BK6_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK6_CH0_INT_LOST_INT_EN)
#define CSIC_BK6_CH1_INT_LOST_INT_EN		9
#define CSIC_BK6_CH1_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK6_CH1_INT_LOST_INT_EN)
#define CSIC_BK6_CH2_INT_LOST_INT_EN		10
#define CSIC_BK6_CH2_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK6_CH2_INT_LOST_INT_EN)
#define CSIC_BK6_CH3_INT_LOST_INT_EN		11
#define CSIC_BK6_CH3_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK6_CH3_INT_LOST_INT_EN)
#define CSIC_BK7_CH0_INT_LOST_INT_EN		12
#define CSIC_BK7_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK7_CH0_INT_LOST_INT_EN)
#define CSIC_BK7_CH1_INT_LOST_INT_EN		13
#define CSIC_BK7_CH1_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK7_CH1_INT_LOST_INT_EN)
#define CSIC_BK7_CH2_INT_LOST_INT_EN		14
#define CSIC_BK7_CH2_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK7_CH2_INT_LOST_INT_EN)
#define CSIC_BK7_CH3_INT_LOST_INT_EN		15
#define CSIC_BK7_CH3_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK7_CH3_INT_LOST_INT_EN)
#define CSIC_BK8_CH0_INT_LOST_INT_EN		16
#define CSIC_BK8_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK8_CH0_INT_LOST_INT_EN)
#define CSIC_BK9_CH0_INT_LOST_INT_EN		20
#define CSIC_BK9_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK9_CH0_INT_LOST_INT_EN)
#define CSIC_BK10_CH0_INT_LOST_INT_EN		24
#define CSIC_BK10_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK10_CH0_INT_LOST_INT_EN)
#define CSIC_BK11_CH0_INT_LOST_INT_EN		28
#define CSIC_BK11_CH0_INT_LOST_INT_EN_MASK	(0X1 << CSIC_BK11_CH0_INT_LOST_INT_EN)

#define CSIC_BK_INTPOOL0_INT_STA0_REG_OFF	0X14C
#define FIFO_AVL_INT_PD				0
#define FIFO_AVL_INT_PD_MASK		(0X1 << FIFO_AVL_INT_PD)
#define FIFO_FULL_INT_PD			1
#define FIFO_FULL_INT_PD_MASK		(0X1 << FIFO_FULL_INT_PD)
#define BK0_CH0_INT_LOST_INT_PD		16
#define BK0_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK0_CH0_INT_LOST_INT_PD)
#define BK0_CH1_INT_LOST_INT_PD		17
#define BK0_CH1_INT_LOST_INT_PD_MASK	(0X1 << BK0_CH1_INT_LOST_INT_PD)
#define BK0_CH2_INT_LOST_INT_PD		18
#define BK0_CH2_INT_LOST_INT_PD_MASK	(0X1 << BK0_CH2_INT_LOST_INT_PD)
#define BK0_CH3_INT_LOST_INT_PD		19
#define BK0_CH3_INT_LOST_INT_PD_MASK	(0X1 << BK0_CH3_INT_LOST_INT_PD)
#define BK1_CH0_INT_LOST_INT_PD		20
#define BK1_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK1_CH0_INT_LOST_INT_PD)
#define BK1_CH1_INT_LOST_INT_PD		21
#define BK1_CH1_INT_LOST_INT_PD_MASK	(0X1 << BK1_CH1_INT_LOST_INT_PD)
#define BK1_CH2_INT_LOST_INT_PD		22
#define BK1_CH2_INT_LOST_INT_PD_MASK	(0X1 << BK1_CH2_INT_LOST_INT_PD)
#define BK1_CH3_INT_LOST_INT_PD		23
#define BK1_CH3_INT_LOST_INT_PD_MASK	(0X1 << BK1_CH3_INT_LOST_INT_PD)
#define BK2_CH0_INT_LOST_INT_PD		24
#define BK2_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK2_CH0_INT_LOST_INT_PD)
#define BK3_CH0_INT_LOST_INT_PD		28
#define BK3_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK3_CH0_INT_LOST_INT_PD)

#define CSIC_BK_INTPOOL0_INT_STA1_REG_OFF	0X150
#define BK4_CH0_INT_LOST_INT_PD		0
#define BK4_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK4_CH0_INT_LOST_INT_PD)
#define BK5_CH0_INT_LOST_INT_PD		4
#define BK5_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK5_CH0_INT_LOST_INT_PD)
#define BK6_CH0_INT_LOST_INT_PD		8
#define BK6_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK6_CH0_INT_LOST_INT_PD)
#define BK6_CH1_INT_LOST_INT_PD		9
#define BK6_CH1_INT_LOST_INT_PD_MASK	(0X1 << BK6_CH1_INT_LOST_INT_PD)
#define BK6_CH2_INT_LOST_INT_PD		10
#define BK6_CH2_INT_LOST_INT_PD_MASK	(0X1 << BK6_CH2_INT_LOST_INT_PD)
#define BK6_CH3_INT_LOST_INT_PD		11
#define BK6_CH3_INT_LOST_INT_PD_MASK	(0X1 << BK6_CH3_INT_LOST_INT_PD)
#define BK7_CH0_INT_LOST_INT_PD		12
#define BK7_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK7_CH0_INT_LOST_INT_PD)
#define BK7_CH1_INT_LOST_INT_PD		13
#define BK7_CH1_INT_LOST_INT_PD_MASK	(0X1 << BK7_CH1_INT_LOST_INT_PD)
#define BK7_CH2_INT_LOST_INT_PD		14
#define BK7_CH2_INT_LOST_INT_PD_MASK	(0X1 << BK7_CH2_INT_LOST_INT_PD)
#define BK7_CH3_INT_LOST_INT_PD		15
#define BK7_CH3_INT_LOST_INT_PD_MASK	(0X1 << BK7_CH3_INT_LOST_INT_PD)
#define BK8_CH0_INT_LOST_INT_PD		16
#define BK8_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK8_CH0_INT_LOST_INT_PD)
#define BK9_CH0_INT_LOST_INT_PD		20
#define BK9_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK9_CH0_INT_LOST_INT_PD)
#define BK10_CH0_INT_LOST_INT_PD		24
#define BK10_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK10_CH0_INT_LOST_INT_PD)
#define BK11_CH0_INT_LOST_INT_PD		28
#define BK11_CH0_INT_LOST_INT_PD_MASK	(0X1 << BK11_CH0_INT_LOST_INT_PD)
/* BK INTPOOL1/2 NOT SUPPORT YET */


/*
 *CSIC CCU registers
 */
#define CSIC_CCU_MODE_REG_OFF			0x000
#define CSIC_MCSI_CLK_MODE			0
#define CSIC_MCSI_CLK_MODE_MASK 		(0X1 << CSIC_MCSI_CLK_MODE)
#define CSIC_MCSI_POST_CLK_MODE 		1
#define CSIC_MCSI_POST_CLK_MODE_MASK		(0X1 << CSIC_MCSI_POST_CLK_MODE)
#define CSIC_CCU_CLK_GATING_DISABLE		31
#define CSIC_CCU_CLK_GATING_DISABLE_MASK	(0X1 << CSIC_CCU_CLK_GATING_DISABLE)

#define CSIC_CCU_PARSER_CLK_EN_REG_OFF  	0x004
#define CSIC_MCSI_PARSER0_CLK_EN		0
#define CSIC_MCSI_PARSER0_CLK_EN_MASK   	(0X1 << CSIC_MCSI_PARSER0_CLK_EN)
#define CSIC_MCSI_PARSER1_CLK_EN		1
#define CSIC_MCSI_PARSER1_CLK_EN_MASK   	(0X1 << CSIC_MCSI_PARSER1_CLK_EN)
#define CSIC_MCSI_COMBO0_CLK_EN 		8
#define CSIC_MCSI_COMBO0_CLK_EN_MASK		(0X1 << CSIC_MCSI_COMBO0_CLK_EN)
#define CSIC_MCSI_MIPI0_CLK_EN  		16
#define CSIC_MCSI_MIPI0_CLK_EN_MASK		(0X1 << CSIC_MCSI_MIPI0_CLK_EN)

#define CSIC_CCU_ISP_CLK_EN_REG_OFF		0x008
#define CSIC_MISP0_CLK_EN			0
#define CSIC_MISP0_CLK_EN_MASK  		(0X1 << CSIC_MISP0_CLK_EN)
#define CSIC_MISP0_BRIDGE_CLK_EN		4
#define CSIC_MISP0_BRIDGE_CLK_EN_MASK   	(0X1 << CSIC_MISP0_BRIDGE_CLK_EN)
#if IS_ENABLED(CONFIG_ARCH_SUN55IW3)
#define CSIC_MISP_MBUS_MEM_RST		8
#define CSIC_MISP_MBUS_MEM_RST_MASK   	(0X1 << CSIC_MISP_MBUS_MEM_RST)
#else
#define CSIC_MISP_MBUS_VE_RST			8
#define CSIC_MISP_MBUS_VE_RST_MASK  		(0X1 << CSIC_MISP_MBUS_VE_RST)
#define CSIC_MISP_MBUS_MEM_RST		9
#define CSIC_MISP_MBUS_MEM_RST_MASK   	(0X1 << CSIC_MISP_MBUS_MEM_RST)
#endif
#define CSIC_MISP0_F2S0_BRIDGE_CH_CLK_EN			12
#define CSIC_MISP0_F2S0_BRIDGE_CH_CLK_EN_MASK  		(0X1 << CSIC_MISP0_F2S0_BRIDGE_CH_CLK_EN)
#define CSIC_MISP0_S2F0_BRIDGE_CH_CLK_EN		    16
#define CSIC_MISP0_S2F0_BRIDGE_CH_CLK_EN_MASK   	(0X1 << CSIC_MISP0_S2F0_BRIDGE_CH_CLK_EN)
#define CSIC_MISP0_BRIDGE_CH_CLK_GATING_DISABLE      20
#define CSIC_MISP0_BRIDGE_CH_CLK_GATING_DISABLE_MASK   	(0X1 << CSIC_MISP0_BRIDGE_CH_CLK_GATING_DISABLE)

#define CSIC_CCU_POST0_CLK_EN_REG_OFF   	0x00c
#define CSIC_MCSI_BK0_CLK_EN			0
#define CSIC_MCSI_BK0_CLK_EN_MASK		(0X1 << CSIC_MCSI_BK0_CLK_EN)
#define CSIC_MCSI_BK1_CLK_EN			1
#define CSIC_MCSI_BK1_CLK_EN_MASK		(0X1 << CSIC_MCSI_BK1_CLK_EN)
#define CSIC_MCSI_BK2_CLK_EN			2
#define CSIC_MCSI_BK2_CLK_EN_MASK		(0X1 << CSIC_MCSI_BK2_CLK_EN)
#define CSIC_MCSI_BK3_CLK_EN			3
#define CSIC_MCSI_BK3_CLK_EN_MASK		(0X1 << CSIC_MCSI_BK3_CLK_EN)
#define CSIC_MCSI_VIPP0_CLK_EN			8
#define CSIC_MCSI_VIPP0_CLK_EN_MASK		(0X1 << CSIC_MCSI_VIPP0_CLK_EN)
#define CSIC_MCSI_VIPP1_CLK_EN			9
#define CSIC_MCSI_VIPP1_CLK_EN_MASK		(0X1 << CSIC_MCSI_VIPP1_CLK_EN)
#define CSIC_MCSI_VIPP2_CLK_EN			10
#define CSIC_MCSI_VIPP2_CLK_EN_MASK		(0X1 << CSIC_MCSI_VIPP2_CLK_EN)
#define CSIC_MCSI_VIPP3_CLK_EN			11
#define CSIC_MCSI_VIPP3_CLK_EN_MASK		(0X1 << CSIC_MCSI_VIPP3_CLK_EN)
#define CSIC_MCSI_POST0_CLK_EN			16
#define CSIC_MCSI_POST0_CLK_EN_MASK		(0X1 << CSIC_MCSI_POST0_CLK_EN)
#if IS_ENABLED(CONFIG_ARCH_SUN55IW3)
#define CSIC_MCSI_POST_MBUS_MEM_RST		20
#define CSIC_MCSI_POST_MBUS_MEM_RST_MASK   	(0X1 << CSIC_MCSI_POST_MBUS_MEM_RST)
#else
#define CSIC_MCSI_POST_MBUS_VE_RST			20
#define CSIC_MCSI_POST_MBUS_VE_RST_MASK  		(0X1 << CSIC_MCSI_POST_MBUS_VE_RST)
#define CSIC_MCSI_POST_MBUS_MEM_RST		21
#define CSIC_MCSI_POST_MBUS_MEM_RST_MASK   	(0X1 << CSIC_MCSI_POST_MBUS_MEM_RST)
#endif

#define CSIC_CCU_CHFREQ_CLOCK_CONTROL_REG_OFF	0X014
#define CSIC_CCU_CHFREQ_CLK_GATING		0
#define CSIC_CCU_CHFREQ_CLK_GATING_MASK		(0X1 << CSIC_CCU_CHFREQ_CLK_GATING)
#define CSIC_CCU_FACTOR_M			8
#define CSIC_CCU_FACTOR_M_MASK			(0X1F << CSIC_CCU_FACTOR_M)
#define CSIC_CCU_FACTOR_N			16
#define CSIC_CCU_FACTOR_N_MASK			(0X1F << CSIC_CCU_FACTOR_N)

#define CSIC_CCU_BK_INTPOOL_CLK_CTRL_REG_OFF   	0x018
#define CSIC_BK_INTPOLL_CLK_GATING			0
#define CSIC_BK_INTPOLL_CLK_GATING_MASK		(0X1 << CSIC_BK_INTPOLL_CLK_GATING)
#define CSIC_BK_FACTOR_M			8
#define CSIC_BK_FACTOR_M_MASK			(0X1F << CSIC_CCU_FACTOR_M)
#define CSIC_BK_FACTOR_N			16
#define CSIC_BK_FACTOR_N_MASK			(0X1F << CSIC_CCU_FACTOR_N)

#endif /* __CSIC__TOP__REG__I__H__ */
